The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to an advancement in a method of improving crystallinity of an element active region to enhance an element characteristic.
An element such as a transistor for constituting a semiconductor device such as an IC (Integrated Circuit) performs a predetermined operation by migration of carriers (electrons or holes) in a semiconductor layer such as Si. Therefore, the characteristics of a semiconductor device largely depends on the crystal state in the element active region.
For example, factors which disturb crystallinity of an Si layer are dislocations, stacking faults, and heavy metals such as Fe or Cu, which are present in the lattice. Since these heavy metals form a recombination center for the carriers, if such heavy metals are present in the element active region, the element characteristics are degraded. In a bipolar transistor, it is assumed that a heavy metal present near a base region causes so-called burst noise (e.g., "Solid State Electronics", 1980, Vol. 23, pp. 1147 to 1149). It is also known that a current amplification characteristic (hFE characteristic) in a low current region is degraded when a crystal defect across a base junction is present.
For this reason, various methods have been conventionally used to improve the crystal state. Especially, a getter method is widely used to remove a heavy metal from the active region.
In the most widely used phosphorus getter method, phosphorus is doped in the rear surface of an Si wafer at a stage after element formation is completed, and high-temperature annealing is performed. The doped phosphorus enters the Si lattice to generate strain, and a force is generated in the crystal to recover an equilibrium state by subsequent annealing, thereby performing the getter effect. That is, the diffusion speed of the above heavy metal is faster than the migration speed of Si. An equilibrium state is obtained such that the heavy metal is captured at the above strain portion.
However, in the case of the phosphorus getter method, the following problems are posed in manufacturing a semiconductor device. Since the phosphorus getter method is performed after element formation, the front surface of the silicon substrate must be prevented from being doped. This requires an extra step of covering the wafer surface with a thick CVD film or the like. In addition, since the phosphorus getter method is normally performed in a POCl.sub.3 diffusion furnace, an impurity such as P.sub.2 O.sub.5 is adhered inside a diffusion tube. The impurity is adhered to the wafer, or a phosphorus mist is scattered in a clean room, thereby adversely affecting manufacture of a semiconductor device.
Furthermore, since a thin insulating film covering the silicon layer surface is formed along with micropatterning of the element in a recent semiconductor device, the phosphorus getter method requiring protection by a thick CVD film cannot be applied.
Recently, argon Ar, carbon C, oxide O, silicon Si, and the like have been ion-implanted to a part of a rear or a front surface of the wafer to damage it, thereby performing an implagetter method using the damaged layer (defect) as a getter site. In this method, the damaged layer is subsequently annealed, and the heavy metal is captured in a process of recovering the equilibrium state.
The implagetter method does not have the abovementioned problems and can advantageously form a getter site selectively at a predetermined region on the front surface of the wafer. However, in order to form a sufficient damaged layer serving as a getter site, a dose of 1.times.10.sup.15 /cm.sup.2 or more is required and ion-implantation must be performed for a long period of time, resulting in an extremely high manufacturing cost. In addition, the getter site formed is generally shallow. For example, the getter site has a depth of 0.3 .mu.m when silicon Si is ion-implanted at 150 keV.
Furthermore, when high-temperature annealing is performed for gettering, a crystal defect of the getter site undesirably expands to a surrounding region. For this reason, even when the getter site is formed in a region such as an isolation diffusion layer of a bipolar semiconductor device which does not adversely affect the element characteristic, the crystal defect sometimes expands to the element active region during the thermal step of gettering.
FIG. 7 is a photograph showing the case in which silicon Si is ion-implanted to the isolation diffusion region under the condition of a dose of 1.times.10.sup.15 /cm.sup.2 to perform gettering. In this photograph, a defect diffusing in an arcuated shape around the isolation region is found.
If such a crystal defect extends to the base junction, the current amplification characteristic (hFE characteristic) is degraded.
In addition, in a method described in U.S. Pat. No. 4063973, Filed: Nov. 4, 1976, a silicon oxide film as an insulating film is formed on a semiconductor substrate, an opening for forming a diffusion region on the silicon oxide film is formed to expose the semiconductor substrate, an As-doped polycrystalline silicon layer is deposited on the exposed surface of the semiconductor substrate and the silicon oxide film, an As-doped silicon oxide film is formed on the polycrystalline silicon layer, an impurity is diffused in an oxide atmosphere at a temperature of 1,100.degree. C. for 30 minutes, and in this diffusion annealing step, a portion of the polycrystalline silicon layer is oxidized to perform impurity diffusion without damaging the surface of the silicon semiconductor substrate.